Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our
Vision, Mission, and 11 Guiding Values
; we affectionately refer to it as the
Aggregate System and it’s won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over
30 years of quarterly profitability
without a great team dedicated to empowering innovation. People like you.
Visit our
careers
page to see what exciting opportunities and company
perks
await!
Job Description:
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Architecture support for development of Low Cost Microchips' FPGA product families.
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Including Architecting IO, Clocking, & interconnect.
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Work with Circuit Design Teams on PPAC tradeoffs, power analysis and optimization.
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Define device floorplan dependencies for IP, based on data flows, block interfaces, power supply & configuration requirements.
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Analyze performance of IP/Fabric subsystems.
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Develop test methodologies for characterizing Single Event Errors (SEE).
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Next generation device families and floorplans.
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Define and support creating device floorplans & collateral required by Marketing, Engineering teams.
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Define device floorplan rules, global interfaces, signals & systems.
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Further development of FPGA internal device-floor planning & visualization toolset.
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Define Package Plans, automation of Package Planning process.
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Ensure high quality and high-performance FPGA product designs with the lowest possible power.
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You will also work with project management to define schedules and highlight risks and issues
As a member of Microchip’s engineering community, you will be responsible for architectural definition, integration, and verification of a complex, product design implemented for many programmable features and modes for use in advanced, low power FPGA devices.
Requirements/Qualifications:
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BSEE 12.5+ years of industry experience/MS 10.5+ years of industry experience or similar technical degree.
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Minimum of several successful previous DDR Memory Controller development efforts.
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Competency in Verilog, System Verilog, and test bench generation and simulation.
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Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.
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Power analysis.
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Ability to support layout, verification, timing characterization, and software model developers.
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Good analytical, oral and written communication skills.
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Able to write clean, readable presentations.
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Self-motivated, proactive team player.
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Ability to work to schedule requirements.
Travel Time:
0% - 25%
Physical Attributes:
Feeling, Hearing, Other, Reaching, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:
90% sitting 10% standing 100% indoors
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the
EEO is the Law Poster
and the
EEO is the Law Poster Supplement
. Please also refer to the
Pay Transparency Policy Statement
.