Job Description

Role - Senior STA / Physical Design Engineer

Location - San Jose, CA (onsite from day 1)

Duration - Fulltime

Job Description:

PD candidates need to have 4nm implementation experience using Cadence tools . Additional DCG synthesis experience is a plus.

STA candidates need to have 4nm Statistical STA experience using Synopsys PrimeTime . Additional Tempus experience is a plus .

PD Lead Engineers Experience: 15+ years

Very good knowledge of Time constraint

CADENCE tools experience

Synopsys tool experience

Low power with Timings / STA Experiences.

Block Level PnR Executions

Low Power Design Knowledge

Chiplet Interface.

Job Type: Full-time

Salary: $180,124.06 - $200,000.00 per year

Experience level:

• 11+ years

Schedule:

• 8 hour shift

Ability to commute/relocate:

• San Jose, CA: Reliably commute or planning to relocate before starting work (Required)

Experience:

• Senior STA / Physical Design Engineer: 10 years (Preferred)
• 4nm implementation experience using Cadence tools: 10 years (Preferred)
• 4nm Statistical STA experience using Synopsys PrimeTime: 10 years (Preferred)
• Additional DCG synthesis experience is a plus.: 10 years (Preferred)
• Additional Tempus experience is a plus .: 10 years (Preferred)
• CADENCE tools: 10 years (Preferred)

Work Location: In person

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